View PSMN8R2-80YS_4681939.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
Rev. 01 -- 25 June 2009 Product data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in LFPAK package qualified to 175 C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment.
1.2 Features and benefits
Advanced TrenchMOS provides low RDSon and low gate charge High efficiency gains in switching power converters Improved mechanical and thermal characteristics LFPAK provides maximum power density in a Power SO8 package
1.3 Applications
DC-to-DC converters Lithium-ion battery protection Load switching Motor control Server power supplies
1.4 Quick reference data
Table 1. VDS ID Ptot Tj Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1 Tmb = 25 C; see Figure 2 Min -55 VGS = 10 V; Tj(init) = 25 C; ID = 75 A; Vsup 80 V; RGS = 50 ; unclamped VGS = 10 V; ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 Typ Max 80 82 130 175 120 Unit V A W C mJ drain-source voltage Tj 25 C; Tj 175 C drain current total power dissipation junction temperature Symbol Parameter
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Dynamic characteristics QGD QG(tot) gate-drain charge total gate charge 12 55 nC nC
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
Quick reference ...continued Conditions VGS = 10 V; ID = 15 A; Tj = 100 C; see Figure 12 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 13; see Figure 12 Min Typ 5.8 Max 13.4 8.5 Unit m m
Table 1.
Symbol Parameter Static characteristics RDSon drain-source on-state resistance
2. Pinning information
Table 2. Pin 1 2 3 4 mb S S S G D Pinning information Symbol Description source source source gate mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G S
1234
SOT669 (LFPAK)
3. Ordering information
Table 3. Ordering information Package Name PSMN8R2-80YS LFPAK Description plastic single-ended surface-mounted package (LFPAK); 4 leads Version SOT669 Type number
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
2 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj Tsld(M) Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature peak soldering temperature source current peak source current Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1 tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 175 C Tj 25 C; Tj 175 C; RGS = 20 k Min -20 -55 -55 Max 80 80 20 57 82 326 130 175 175 260 Unit V V V A A A W C C C
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode IS ISM EDS(AL)S 82 326 120 A A mJ
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 75 A; Vsup 80 V; drain-source avalanche RGS = 50 ; unclamped energy
80 ID (A) 60
003aad260
120 Pder (%) 80
03aa16
40
40
20
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 Tmb (C) 200
Fig 1.
Normalized continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
3 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
103 ID (A) 102 100 s 10 DC Limit RDSon = VDS / ID 10 s
003aad315
1
1ms 10ms 100ms
10-1 1 10
102
VDS (V)
103
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
4 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter thermal resistance from junction to mounting base Conditions see Figure 4 Min Typ Max 1.1 Unit K/W
10 Zth(j-mb) (K/W) 1 = 0.5 10-1
003aac456
0.2 0.1 0.05 0.02
P = tp T
10-2
single shot
tp T
t
10-3 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
5 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = -55 C ID = 250 A; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = 175 C; see Figure 10; see Figure 11 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 10; see Figure 11 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 10; see Figure 11 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 80 V; VGS = 0 V; Tj = 25 C VDS = 80 V; VGS = 0 V; Tj = 125 C VGS = -20 V; VDS = 0 V; Tj = 25 C VGS = 20 V; VDS = 0 V; Tj = 25 C VGS = 10 V; ID = 15 A; Tj = 175 C; see Figure 12 VGS = 10 V; ID = 15 A; Tj = 100 C; see Figure 12 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 13; see Figure 12 RG internal gate resistance f = 1 MHz (AC) total gate charge gate-source charge pre-threshold gate-source charge post-threshold gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time VDS = 40 V; RL = 1.6 ; VGS = 10 V; RG(ext) = 4.7 ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 ID = 25 A; VDS = 40 V; see Figure 15; see Figure 14 VDS = 40 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 16 ID = 0 A; VDS = 0 V; VGS = 10 V ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14 Min 73 80 1 2 Typ 3 5.8 0.74 Max 4.6 4 4 50 100 100 20 13.4 8.5 Unit V V V V V A A nA nA m m m
Static characteristics
Dynamic characteristics QG(tot) QGS QGS(th) QGS(th-pl) QGD VGS(pl) Ciss Coss Crss td(on) tr td(off) tf 48 55 15 10 5 12 4.5 3640 390 180 25 22 51 16 nC nC nC nC nC nC V pF pF pF ns ns ns ns
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
6 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
Table 6. Symbol VSD trr Qr
[1]
Characteristics ...continued Parameter source-drain voltage reverse recovery time recovered charge Conditions IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 17 IS = 50 A; dIS/dt = 100 A/s; VGS = 0 V; VDS = 40 V Min Typ 0.81 55 106 Max 1.2 Unit V ns nC
Source-drain diode
Tested to JEDEC standards where applicable.
80 ID (A) 60
003aad172
20 10 8 6
5
6000 C (pF)
003aad178
Ciss
4000 4.5 40 Crss 2000 20 VGS (V) = 4
0 0 0.5 1 1.5 VDS (V) 2
0 0 3 6 9 VGS (V) 12
Fig 5.
Output characteristics: drain current as a function of drain-source voltage; typical values
80
003aad174
Fig 6.
Input and reverse transfer capacitances as a function of gate-source voltage; typical values
003aad179
100 gfs (S) 80
ID (A) 60
60
40 Tj = 150 C 20
40
Tj = 175 C
Tj = 25 C
20
0 0 2 4 VGS (V) 6
0 0 20 40 60 ID (A) 80
Fig 7.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
Fig 8.
Forward transconductance as a function of drain current; typical values
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
7 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
25 RDSon (m) 20
003aad180
10-1 ID (A) 10-2 min typ max
03aa35
10-3
15
10-4
10
10-5
5 0 5 10 15 VGS (V) 20
10-6 0 2 4 VGS (V) 6
Fig 9.
Drain-source on-state resistance as a function of gate-source voltage; typical values
5
003aad280
Fig 10. Sub-threshold drain current as a function of gate-source voltage
2.5 a
003aad045
VGS(th) (V) 4 max
2.0
3
typ
1.5
2
min
1.0
1
0.5
0 -60
0
60
120 Tj (C)
180
0.0 -60
-30
0
30
60
90
120
150 180 Tj (C)
Fig 11. Gate-source threshold voltage as a function of junction temperature
Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
8 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
10 RDSon (m) 9 VGS (V) = 5
003aad173
VDS ID
5.5
VGS(pl)
8 6 7 8 10 6 20
VGS(th) VGS QGS1 QGS2 QGD QG(tot)
003aaa508
QGS
5 0 30 60 ID (A) 90
Fig 14. Gate charge waveform definitions
Fig 13. Drain-source on-state resistance as a function of drain current; typical values
10 VGS (V) 8 64V 16V VDS = 40V 103 4 Coss 2 Crss 0 0 20 40 QG (nC) 60 102 10-1
003aad176
104 C (pF)
003aad177
Ciss
6
1
10
VDS (V)
102
Fig 15. Gate-source voltage as a function of gate charge; typical values
Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
9 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
100 IS (A) 80
003aad175
60 Tj = 150 C 40 Tj = 175 C Tj = 25 C
20
0 0 0.3 0.6 0.9 VSD (V) 1.2
Fig 17. Source current as a function of source-drain voltage; typical values
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
10 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
E b2 L1
A c2
A2
C E1 b3
mounting base D1 H D
b4
L2
1
e
2
3
b
1/2
4
wM A c X
e
A A1 C
(A 3)
detail X L yC 0 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0
1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62
0.25 0.30 4.10 4.20 0.19 0.24 3.80
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16
Fig 18. Package outline SOT669 (LFPAK)
PSMN8R2-80YS_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
11 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
8. Revision history
Table 7. Revision history Release date 20090625 Data sheet status Product data sheet Change notice Supersedes Document ID PSMN8R2-80YS
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
12 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN8R2-80YS_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
13 of 14
NXP Semiconductors
PSMN8R2-80YS
N-channel LFPAK 80 V 8.5 m standard level MOSFET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 June 2009 Document identifier: PSMN8R2-80YS_1

▲Up To Search▲

Price & Availability of PSMN8R2-80YS

	To Download PSMN8R2-80YS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .